The present invention relates generally to frequency synthesizers having at least one programmably characterized phase lock loop (PLL) circuit, and more particularly, to a frequency synthesizer including a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of a PLL circuit among the at least one PLL circuit, the buffer memory, and the central controller.
Contemporary frequency synthesizers, like the type manufactured by Plessey Semiconductors, model number NJ88C31, for example, include a PLL circuit and at least one register which is dynamically programmable with data words for uniquely characterizing the PLL circuit in its generation of a synthesized channel frequency signal. The at least one register may include a shift register governed by an external clock signal for serially receiving a data word from a single data line, and at least one latching register for transferring, in response to an external data transfer signal, the data word in parallel from the shift register to the PLL circuit for operational characterization thereof.
Conventionally, frequency synthesizers of the aforementioned type may be, at times, controlled by a central controller, which may be a microcomputer, for example, generally utilizing a serial peripheral interface thereof. In such systems, the serial peripheral interface of the microcomputer would be dedicated to the frequency synthesizer for serially transferring a data word thereto to uniquely characterize the frequency synthesizer in its generation of a synthesized channel frequency signal. Accordingly, the central controller is burdened with accomplishing each serial data stream transfer which could be quite time consuming, especially in radio receiver operations, like channel searching, for example.
In some cases, the frequency synthesizers may include a plurality of PLL circuits, each having its own programmable characterization circuitry and each requiring a serial peripheral interface from the central controller. Most central controllers do not have a plurality of serial peripheral interfaces and/or cannot afford to dedicate such for the sole use of characterizing the PLL circuits of a frequency synthesizer, although some central controllers do permit timesharing of a peripheral interface among a plurality of peripheral devices. For an example of a frequency synthesizer having a plurality of PLL circuits, reference may be made to the copending patent application bearing Ser. No. 345,809; filed May 1, 1989 by Herold et al. entitled "A Frequency Synthesizer with Dynamically Programmable Frequency Range of Selected Loop Bandwidth"; and assigned to the same assignee as the instant application.
The present invention offers an interface controller for a frequency synthesizer having at least one PLL circuit programmably characterized to generate a channel frequency signal, which interface controller is intended to alleviate the above described limitations of programmably characterizing such PLL circuits.